Exemplary embodiments of the present invention relate to a method for fabricating a highly integrated semiconductor memory apparatus, and more particularly, to a method for fabricating a semiconductor memory apparatus capable of reducing defects by increasing a processing margin when forming transistors in the highly integrated semiconductor memory apparatus.
In general, a semiconductor memory apparatus includes a plurality of unit cells, each of which consists of a capacitor and a transistor. The capacitor is used to temporarily store data, and the transistor is used to transmit data between a bit line and the capacitor in response to a control signal, e.g., a voltage level of a word line, using a property of semiconductor whose electrical conductivity changes depending on the environment. The transistor includes three regions of a gate, a source and a drain, and charge movement between the source and the drain occurs depending on the control signal inputted to the gate. The charge movement between the source and the drain is performed through a channel region.
In case of forming a typical transistor using a semiconductor substrate, a gate is formed on the semiconductor substrate, and a source and a drain are formed by doping impurities into portions of the semiconductor substrate at both sides of the gate. However, as the data storage capacity and the degree of integration of a semiconductor memory apparatus increase, the size of each unit cell is required to be smaller. That is, the design rule of a capacitor and a transistor included in the unit cell has been reduced, and thus a channel length of the cell transistor has been gradually decreased. As a result, a short channel effect and drain induced barrier lower (DIBL) have occurred in the typical transistor, which deteriorated the operational reliability of the transistor. The above drawbacks occurring as a result of the reduction of the channel length can be overcome by maintaining a threshold voltage to allow the cell transistor to perform a normal operation. In general, as the channel length of the transistor has been made smaller, the doping concentration of impurities in a region where a channel is formed has been increased.
However, as the design rule goes less than 100 nm, further increasing the doping concentration in the channel region as much as the extent of the reduction of the design rule increases an electric field in a storage node (SN) junction. As a result, it may cause another drawback that a refresh property of the semiconductor memory apparatus is deteriorated. To overcome this drawback, a cell transistor having a three-dimensional channel structure is employed to maintain a channel length thereof, although the design rule is reduced. In the three-dimensional channel structure, a long channel is formed in a vertical direction. Namely, since the channel length is secured in the vertical direction although a channel width is small in a horizontal direction, the doping concentration may be reduced, and thus the deterioration of the refresh property may be minimized.
Meanwhile, as the degree of integration of the semiconductor memory apparatus is getting higher, the distance between a bit line and a word line that are coupled to the cell transistor becomes smaller. As a result, parasitic capacitance generated between the bit line and the word line increases, and the increasing parasitic capacitance deteriorates an operational margin of a sense amplifier amplifying data transmitted through the bit line. This is fatal to the operational reliability of the semiconductor memory apparatus. In order to solve the above drawbacks, a buried word line structure has been introduced to reduce the parasitic capacitance between the bit line and the word line. In the buried word line structure, the word line is formed only in a recess not over the semiconductor substrate. Hereinafter, a method for fabricating the semiconductor memory apparatus employing the buried word line structure will be described.
FIGS. 1a and 1b are plane views illustrating masks used in fabricating a typical semiconductor memory apparatus. In particular, FIG. 1a shows a mask 110 defining a buried word line included in a cell region of the semiconductor memory apparatus and FIG. 1b describes a mask 120 defining a gate pattern formed in a peripheral region and a bit line formed in the cell region of the semiconductor memory apparatus.
Referring to FIG. 1a, the buried word line mask 110 includes a first region 112 to define a pattern to be formed in the cell region and a second region 116 to define a pattern to be formed in the peripheral region. The first region 112 includes a plurality of line patterns 114 each of which defines a buried word line, whereas no pattern is defined in the second region 116.
Although it is not shown, in the cell region, after forming an isolation region in a semiconductor substrate using a mask defining an active region, a recess (not shown) is formed in the active region using the buried word line mask 110, and then the buried word line is formed by filling the recess with a conductive material. However, when forming the recess to form the buried word line in the cell region, no pattern is formed in the peripheral region. This is because any transistor including a recess gate or a buried gate is not formed in the peripheral region, and a transistor having a two-dimensional plane channel is formed in the peripheral region.
Referring to FIG. 1b, the bit line and gate pattern mask 120 includes a first region 122 and a second region 126. The first region 122 includes line patterns 124 to define a bit line to be formed in the cell region. The second region 126 includes a first line pattern 128 to define the gate pattern to be formed in the peripheral region, a second line pattern 127 to define a dummy gate pattern, and a pad pattern 129 to define a connection pad coupled to the gate pattern. That is, when fabricating the semiconductor memory apparatus using the bit line and gate pattern mask 120, the bit line included in the cell region and the gate pattern included in the peripheral region are formed at substantially the same height.
FIGS. 2a and 2b are cross-sectional views and a solid view illustrating the semiconductor memory apparatus fabricated using the masks described in FIGS. 1a and 1b, respectively.
Referring to FIGS. 2a to 2b, in the cell region of the semiconductor memory apparatus, an isolation layer 206 defining an active region 204 is formed in a semiconductor substrate 200, and buried word lines 202 are formed in two recesses that are formed in the active region 204 using the buried word line mask 110. After forming an insulation layer 208 on the buried word lines 202 and the active region 204, a bit line 210 partially coupled to the active region 204 is formed by etching a portion of the insulation layer 208 to partially expose the top surface of the active region 204.
In the meantime, although the isolation layer 206 is also formed in the peripheral region of the semiconductor memory apparatus like in the cell region, a gate pattern 212, not the buried word line 202, is formed on the active region 204 of the peripheral region. Referring to FIG. 2b illustrating a cross-sectional view of the gate pattern 212 in a minor axial direction, i.e., a cross-sectional view taken along an I-I′ line, the gate pattern 212 is formed on a two-dimensional plane channel region, and a dummy gate pattern 218 shown in FIG. 2d is formed on the isolation layer 206 in the peripheral region, whereas the buried word line 202 is formed on a three-dimensional channel region in the cell region. Furthermore, referring to FIG. 2c illustrating a cross-sectional view of the gate pattern 212 in a major axial direction, i.e., a cross-sectional view taken along an II-II′ line, a connection pad 214 coupled to an end of the gate pattern 212 is formed on the isolation layer 206.
FIG. 2d is a solid view illustrating a transistor included in the peripheral region of the semiconductor memory apparatus. The active region 204 defined by the isolation layer 206 described in FIG. 2a has an island shape. The gate pattern 212 is formed on the active region 204, and the connection pad 214 is formed at the end of the gate pattern 212 to transfer a gate voltage. At this time, the gate pattern 212 and the connection pad 214 formed using the bit line and gate pattern mask 120 are disposed at substantially the same height and constructed with one pattern having a ‘T’ shape. Since the connection pad 214 and the active region 204 should be a certain distance apart to suppress the generation of the parasitic capacitance and the electrical short, the gate pattern 212 should be formed extending onto the isolation layer 206 as well as onto the active region 204. After then, a plurality of contacts 216 is formed on the active region 204 and the connection pad 214 to transmit signals and data or to supply the gate voltage.
Particularly looking at a process of forming the contacts 216, an inter-layer insulation layer (not shown) is deposited on the gate pattern 212 and the connection pad 214, and contact holes (not shown) are formed and filled with a conductive material. Herein, since a contact hole formed on the connection pad 214 has a depth different from that of a contact hole formed on the active region 204, a processing margin of the contact hole formed on the active region 204 may be reduced, wherein the depth of the contact hole formed on the active region 204 is greater than that of the contact hole formed on the connection pad 214. That is, in case the active region 204 is not fully exposed by the contact hole because the depth of the contact hole formed on the active region 204 is greater, the contact resistance between the active region 204 and the contact 216 may increase.
FIG. 3 is a plane view illustrating the transistor described in FIG. 2D.
Referring to FIG. 3, the active region 204 is defined by the isolation layer 206; the gate pattern 212 is formed on the active region 204; and the connection pad 214 is formed on the isolation layer 206. Moreover, the plurality of contacts 216 is formed on the active region 204 and the connection pad 214.
The dummy gate patterns 218 are further formed on the isolation layer 206. Recently, as the design rule decreases, the line width of the gate pattern 212 formed in the peripheral region is also reduced. As a result, the processing margin of the gate pattern 212 is decreasing. To overcome this drawback, the dummy gate patterns 218 are additionally formed around the gate pattern 212 to allow the gate pattern 212 to be formed with a uniform line width.
However, while the gate pattern 212 is formed in a long shape to be directly coupled to the connection pad 214 as shown in a pad connection region ‘A’ of FIG. 3, the dummy gate patterns 218 cannot be formed close to the connection pad 214. This is because all of the dummy gate patterns 218, the gate pattern 212 and the connection pad 214 are formed at substantially the same height, and thus a defect that the dummy gate patterns 218 are coupled to the connection pad 214 may occur in case of forming the dummy gate patterns 218 close to the connection pad 214. Therefore, it is difficult to insert the dummy gate patterns 218 and the gate pattern 212 in substantially the same length. When inserting the dummy gate patterns 218, it is difficult to uniformly maintain the line width of the gate pattern 212 in the pad connection region ‘A’ where the gate pattern 212 is coupled with the connection pad 214. In case the line width of the gate pattern 212 formed in the peripheral region is not uniform or the coupling between the connection pad 214 and the gate pattern 212 is damaged, the resistance increases. As a result, an operating speed may be reduced, or the operational stability may be deteriorated.